Selection transistors of non-volatile memory devices are connected to a memory transistor and perform a function to provide access to the memory transistor. As shown in FIG. 1, NAND-type flash memory devices are typical non-volatile memory devices having selection transistors that have a cell string structure made up of a couple of selection transistors and memory transistors between the selection transistors. The selection transistors may be classified into a ground selection transistor and a string selection transistor. A NAND-type cell array may comprise a plurality of cell strings and may include a ground selection line GSL, a string selection line SSL, and a word line WL crossing the cell strings. A gate electrode of a memory transistor is connected to the word line WL, and a ground selection transistor and the string selection transistor are respectively connected to the ground selection line GSL and the string selection line SSL.
FIGS. 2A and 2B respectively show a channel voltage of a memory cell transistor of a selected cell string and a non-selected cell string in a write operation. Referring to FIGS. 2A and 2B, 0 volts are applied to the ground selection line GSL, 0 volts are applied to the string selection line SSL and the selected bit line, and Vcc is applied to the non-selected bit line. In addition, a high program voltage (e.g. approximately 18 volts) is applied to the selected word line, and a pass voltage Vpass capable of turning on a memory transistor is applied to the non-selected word line. The memory transistor is selected by the selected word line and the non-selected word line. As shown in FIG. 2A, in the selected memory transistor, a program voltage (e.g., approximately 18 volts) is applied to a gate electrode, and 0 volts are applied to a channel to be programmed by F-N tunneling. A channel is floating in the memory cell transistor of the non-selected cell string connected to the selected word line so that even though a program voltage is applied to the gate electrode, the channel voltage is boosted about 8 volts so as to inhibit programming.
However, when the selected memory transistor is programmed, there is a possibility that the non-selected memory transistor sharing the selected word line is programmed. This abnormal program may be caused by a memory transistor connected to the selected word line. As previously mentioned, to prevent the selected memory transistor form being programmed, it is necessary for the channel voltage to be boosted to suppress the program irrespective of the application of the program voltage to the gate electrode. However, if the channel voltage is not boosted, then an abnormal program may occur. As shown in FIGS. 3A and 3B, when 18 volts and 0 volts are respectively applied to the gate electrode and the channel of the selected memory transistor to be programmed, the channel voltage of the non-selected memory transistor frequently remains around 0 volts. In other words, the channel of the non-selected memory transistor is not floating by forming a current path under any circumstance.
A cell string of the NAND-type cell array is floated by a selection transistor. Accordingly, if there is a channel leakage in the selection transistor, this function may be performed abnormally. The above abnormal program may become more serious with decreasing channel length of the transistor. After considering all the factors, leakage current is generated by punch-through with decreasing channel length of the selection transistor. As a result, the channel of the non-selected cell string may not float, which may impair voltage boosting.